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Design Rule Verification Report

Date : 6/28/2011
Time : 5:43:53 PM
Elapsed Time : 00:00:01
Filename : C:\Documents and Settings\Administrator\My Documents\Hardware SID\bigpcb.PcbDoc
Warnings : 0
Rule Violations : 49

Summary

Warnings Count
Total 0

Rule Violations Count
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Hole Size Constraint (Min=1mil) (Max=100mil) (All) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=10mil) (All),(All) 7
Silkscreen Over Component Pads (Clearance=10mil) (All),(All) 3
Silk to Silk (Clearance=10mil) (All),(All) 15
Net Antennae (Tolerance=0mil) (All) 0
Width Constraint (Min=12mil) (Max=12mil) (Preferred=12mil) (All) 0
Clearance Constraint (Gap=13mil) (All),(All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Room retro (Bounding Region = (6045mil, 3065mil, 12495mil, 5235mil) (InComponentClass('retro')) 24
Total 49

Minimum Solder Mask Sliver (Gap=10mil) (All),(All)
Via (2459mil,4983mil) Top Layer to Bottom Layer Pad C3-2(2395mil,4950mil) Multi-Layer
Via (5700mil,4593.874mil) Top Layer to Bottom Layer Pad U7-28(5775mil,4580mil) Multi-Layer
Via (4275mil,5328mil) Top Layer to Bottom Layer Pad U6-5(4210.984mil,5365.038mil) Multi-Layer
Via (4137mil,4665mil) Top Layer to Bottom Layer Pad U6-12(4210.984mil,4665.038mil) Multi-Layer
Via (4455mil,3960mil) Top Layer to Bottom Layer Pad U4-9(4515mil,3910mil) Multi-Layer
Via (4455mil,3960mil) Top Layer to Bottom Layer Pad U4-8(4515mil,4010mil) Multi-Layer
Via (4063mil,4988mil) Top Layer to Bottom Layer Via (4085mil,5063mil) Top Layer to Bottom Layer
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Silkscreen Over Component Pads (Clearance=10mil) (All),(All)
Text "U1" (2160.922mil,3844mil) Top Overlay Pad C8-1(2166.574mil,3925mil) Multi-Layer
Text "C6" (4942mil,5494mil) Top Overlay Pad C4-1(5025mil,5526.574mil) Multi-Layer
Text "C8" (2145.5mil,4037.5mil) Top Overlay Pad U2-9(2210mil,4120mil) Multi-Layer
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Silk to Silk (Clearance=10mil) (All),(All)
Text "U1" (2160.922mil,3844mil) Top Overlay Arc (2265mil,3925mil) Top Overlay
Text "C6" (4942mil,5494mil) Top Overlay Arc (5025mil,5625mil) Top Overlay
Text "C10" (3505.5mil,3292.5mil) Top Overlay Arc (3605mil,3312.362mil) Top Overlay
Text "C11" (4018mil,3292.5mil) Top Overlay Arc (4135mil,3312.362mil) Top Overlay
Text "C9" (4530.5mil,3292.5mil) Top Overlay Arc (4665mil,3312.362mil) Top Overlay
Text "C2" (3011.5mil,5368.5mil) Top Overlay Track (3005mil,5410mil)(3005mil,5860mil) Top Overlay
Text "C2" (3011.5mil,5368.5mil) Top Overlay Track (3005mil,5410mil)(3155mil,5410mil) Top Overlay
Text "U4" (4491.5mil,4141.5mil) Top Overlay Track (4257.048mil,4174.486mil)(4764.922mil,4174.486mil) Top Overlay
Text "C10" (3505.5mil,3292.5mil) Top Overlay Track (3630mil,3312.362mil)(3709.332mil,3312.362mil) Top Overlay
Text "C10" (3505.5mil,3292.5mil) Top Overlay Track (3500.67mil,3312.362mil)(3580mil,3312.362mil) Top Overlay
Text "C10" (3505.5mil,3292.5mil) Top Overlay Track (3500.67mil,3312.362mil)(3500.67mil,4107.638mil) Top Overlay
Text "C11" (4018mil,3292.5mil) Top Overlay Track (4030.67mil,3312.362mil)(4110mil,3312.362mil) Top Overlay
Text "C11" (4018mil,3292.5mil) Top Overlay Track (4030.67mil,3312.362mil)(4030.67mil,4107.638mil) Top Overlay
Text "C9" (4530.5mil,3292.5mil) Top Overlay Track (4560.67mil,3312.362mil)(4640mil,3312.362mil) Top Overlay
Text "C9" (4530.5mil,3292.5mil) Top Overlay Track (4560.67mil,3312.362mil)(4560.67mil,4107.638mil) Top Overlay
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Room retro (Bounding Region = (6045mil, 3065mil, 12495mil, 5235mil) (InComponentClass('retro'))
Room Definition Between Component on TopLayer And Rule on TopLayer
Room Definition Between Component on TopLayer And Rule on TopLayer
Room Definition Between Component on TopLayer And Rule on TopLayer
Room Definition Between Component on TopLayer And Rule on TopLayer
Room Definition Between Component on TopLayer And Rule on TopLayer
Room Definition Between Component on TopLayer And Rule on TopLayer
Room Definition Between Component on BottomLayer And Rule on TopLayer
Room Definition Between Component on TopLayer And Rule on TopLayer
Room Definition Between Component on TopLayer And Rule on TopLayer
Room Definition Between Component on TopLayer And Rule on TopLayer
Room Definition Between Component on TopLayer And Rule on TopLayer
Room Definition Between Component on TopLayer And Rule on TopLayer
Room Definition Between Component on TopLayer And Rule on TopLayer
Room Definition Between Component on TopLayer And Rule on TopLayer
Room Definition Between Component on TopLayer And Rule on TopLayer
Room Definition Between Component on TopLayer And Rule on TopLayer
Room Definition Between Component on TopLayer And Rule on TopLayer
Room Definition Between Component on TopLayer And Rule on TopLayer
Room Definition Between Component on TopLayer And Rule on TopLayer
Room Definition Between Component on TopLayer And Rule on TopLayer
Room Definition Between Component on TopLayer And Rule on TopLayer
Room Definition Between Component on TopLayer And Rule on TopLayer
Room Definition Between Component on TopLayer And Rule on TopLayer
Room Definition Between Component on TopLayer And Rule on TopLayer
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